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just your average ordinary everyday superhero
🦸‍♂️
just your average ordinary everyday superhero
356 followers · 70 following

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@howerj
Richard James Howe howerj
Software Engineer - looking for contract work!

10000 subleq ltd UK

@MJoergen
Michael Jørgensen MJoergen
Experienced software and firmware developer. Primary focus is with embedded applications in telecommunications, see my LinkedIn profile.

Weibel Scientific Denmark

@LukasP46
Lukas Pajak LukasP46

Germany

@Unike267
Unai Sainz-Estebanez Unike267
The silicon age. In our pockets 📱 In our brains 🧠 In our hearts 💕

Bizkaia

@electronicarts
Electronic Arts electronicarts
Electronic Arts, inspiring a global community of players to explore new ways to play every day

Worldwide

@JimLewis
Jim Lewis JimLewis
VHDL Verification Specialist, OSVVM author, VHDL Trainer (including on OSVVM), IEEE VHDL WG Chair, Yoga Teacher

SynthWorks / OSVVM Tigard, OR

@hVHDL
hVHDL
@jesseopdenbrouw
Jesse op den Brouw jesseopdenbrouw
I am a teacher at The Hague University of Applied Sciences, teaching Digital Systems and Microcontrollers. Currently working on RISC-V bare metal processors.

THUAS Delft, The Netherlands

@colognechip
Cologne Chip AG colognechip

Cologne, Germany

@pu-cc
Patrick Urban pu-cc

Cologne Chip AG Köln, Germany

@OpenPOWERFoundation
OpenPOWER Foundation OpenPOWERFoundation
OpenPOWER Foundation - Public facing mirror

In the POWER Cloud

@Dasharo
Dasharo Dasharo
We are crafting a scalable, modular, and easy to combine BIOS firmware technology to help you improve your products without boundaries on processor architecture

Gdańsk, Poland

@jue89
Juergen Fitschen jue89
DL4JUE

SSV Software Systems GmbH Germany

@mikaelsky
Mikael Mortensen mikaelsky
20+ years of ASIC development. Systems and Processor Architect.

Skyworks Solutions Inc San Jose

@gabriele-galeotti
Gabriele Galeotti gabriele-galeotti
HW/SW engineer
@The-OpenROAD-Project
The OpenROAD Project The-OpenROAD-Project
OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source layout generation flow (RTL-to-GDS).

United States of America

@regymm
regymm regymm
Post-undergrad amateur programmer

Univ. of Sci. & Tech. of China Forever

@fossi-foundation
FOSSi Foundation fossi-foundation
The FOSSi Foundation exists to promote and protect the open source silicon chip movement.
@x653
x653
@VHDL
Open Source VHDL Group VHDL
@Cortana4
Cortana4
@NessieCircuits
NessieCircuits
@NikLeberg
NikLeberg

Switzerland

@dnltz
Daniel Schultz dnltz

@phytec Wiesbaden

@crolfes
crolfes

Fraunhofer IMS Duisburg, Germany

@gregdavill
Greg Davill gregdavill

Australia

@riscv-software-src
RISC-V Software riscv-software-src
The Open-Standard Instruction Set Architecture

Switzerland

@riscv-collab
RISC-V Collaboration riscv-collab
The Open-Standard Instruction Set Architecture

Switzerland

@riscv-non-isa
RISC-V Non-ISA Specifications riscv-non-isa
The Open-Standard Instruction Set Architecture

Switzerland

@Fraunhofer-IMS
Fraunhofer IMS Fraunhofer-IMS
Fraunhofer Institute for Microelectronic Circuits and Systems

Germany

@antmicro
Antmicro antmicro
Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems.
@WillGreen
Will Green WillGreen
Public stuff is mostly FPGA and RISC-V.
@ThomasHornschuh
Thomas Hornschuh ThomasHornschuh

The Bonfire Project Heidelberg, Germany

@nickg
Nick Gasson nickg
@tgingold
tgingold
@hamsternz
Mike Field hamsternz

Hamsterworks Chirstchurch, New Zealand

@mattvenn
Matt Venn mattvenn
Engineer and Science Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member.

@YosysHQ-GmbH @TinyTapeout Valencia, Spain

@imphil
Philipp Wagner imphil

@fossi-foundation @IBM Augsburg, DE

@htminuslab
Hans Tiggeler htminuslab
FPGA/Embedded/EDA support engineer. From TMS9900 to RISC-V.
@airhdl
airhdl airhdl
Web-based VHDL/SystemVerilog AXI4 register generator for FPGA and ASIC projects.

Germany

@machdyne
Machdyne UG machdyne
Timeless computers, modules and tools.
@hipolitoguzman
Hipólito Guzmán-Miranda hipolitoguzman
Professor at Universidad de Sevilla, Department of Electronic Engineering. Design and verification of digital circuits.

Universidad de Sevilla Sevilla, Spain

@PLC2
PLC2 GmbH PLC2
Programmable Logic Competence Center

Freiburg, Germany

@LarsAsplund
Lars Asplund LarsAsplund
@VUnit
VUnit
@Paebbels
Patrick Lehmann Paebbels
Vice-Chair of the IEEE P1076 Working Group (VHDL Analysis and Standardization Group- VASG). I'm a VHDL expert and FPGA-technology trainer at @PLC2.

@PLC2 Bötzingen, Germany

@akaeba
Andreas akaeba
Electronic Designer; Script Engineer; Multilingualist

Chemnitz, Saxony, Germany

@fontamsoc
fontamsoc
RISC-V RTOS-enabled multi-core SoC with Wishbone4 peripherals.
@tinyvision-ai-inc
tinyVision.ai Inc. tinyvision-ai-inc
@colinoflynn
Colin O'Flynn colinoflynn
Colin is a huge nerd.

@newaetech Halifax, Canada

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