stnolting

🦸‍♂️

just your average ordinary everyday superhero

stnolting

🦸‍♂️

just your average ordinary everyday superhero

Roads? Where we're going we don't need roads. - "Doc" Emmett L. Brown

354 followers · 70 following

@Fraunhofer-IMS
🇪🇺 European Union

neorv32 Public

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller embedded cpu fpga processor vhdl riscv

VHDL 1,786 266 BSD 3-Clause "New" or "Revised" License 1 issue needs help Updated Jun 13, 2025
neorv32-micropython Public

🐍 Port of MicroPython for the NEORV32 RISC-V Processor.

python microcontroller embedded micropython risc-v neorv32

C 2 MIT License Updated Jun 9, 2025
neorv32-freertos Public

💾 FreeRTOS port for the NEORV32 RISC-V Processor.

embedded freertos rtos risc-v neorv32

9 4 MIT License Updated Jun 9, 2025
neorv32-vunit Public

🔍 Simulating the NEORV32 RISC-V Processor using the VUnit testing framework.

testing simulation verification vunit neorv32

VHDL 1 2 BSD 3-Clause "New" or "Revised" License Updated Jun 9, 2025
neorv32-setups Public

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

fpga vhdl intel verilog xilinx lattice soc

VHDL 79 26 BSD 3-Clause "New" or "Revised" License Updated Jun 9, 2025
neorv32-verilog Public template

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

VHDL 90 18 BSD 3-Clause "New" or "Revised" License Updated Jun 9, 2025
neorv32-riscof Public template

✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

processor vhdl verification riscv isa ghdl risc-v

Python 34 8 BSD 3-Clause "New" or "Revised" License Updated Jun 9, 2025
neoTRNG Public

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

cryptography asic fpga entropy random vhdl chaos

VHDL 189 23 BSD 3-Clause "New" or "Revised" License Updated Jun 6, 2025
riscv-gcc-prebuilt Public archive

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

linux gcc riscv risc-v prebuilt-binaries rv32i neorv32

Shell 103 12 GNU General Public License v2.0 Updated Feb 22, 2025
riscv-arch-test Public
Forked from riscv-non-isa/riscv-arch-test

Assembly 1 Apache License 2.0 Updated Nov 6, 2024
vhpi_jtag Public
Forked from NikLeberg/cosim_jtag

Connect to your GHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> vhpi_jtag <-VHPI-> GHDL

C 2 MIT License Updated Aug 13, 2024
icarus-verilog-prebuilt Public archive

📦 Prebuilt Icarus Verilog simulator package for x64 Linux.

linux simulator asic fpga verilog icarus-verilog hdl

2 GNU General Public License v2.0 Updated Mar 16, 2024
neorv32_soc Public
Forked from NikLeberg/neorv32_soc

Playing around with the [`neorv32`](https://github.com/stnolting/neorv32) SoC on a [Gecko4Education](https://gecko-wiki.ti.bfh.ch/gecko4education:start) Board with an Intel Cyclone IV E FPGA.

VHDL 2 1 MIT License Updated Aug 27, 2023
neorv32-formal Public archive

Formal verification (experiments) targeting the NEORV32 RISC-V processor.

VHDL 7 2 BSD 3-Clause "New" or "Revised" License Updated Feb 1, 2023
riscv-debug-dtm Public archive

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

vhdl gdb debug risc-v openocd jtag neorv32

VHDL 26 4 BSD 3-Clause "New" or "Revised" License Updated Jan 6, 2023
fpga_puf Public archive

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

security fpga authentication vhdl fingerprint key-generation puf

VHDL 132 21 BSD 3-Clause "New" or "Revised" License Updated Nov 5, 2022
fpga_torture Public archive

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

fpga vhdl stress-testing power lfsr utilization

VHDL 29 4 BSD 3-Clause "New" or "Revised" License Updated Aug 20, 2022
captouch Public archive

👇 Add capacitive touch buttons to any FPGA!

fpga vhdl button keypad capacitive-touch-sensor fomu

VHDL 103 10 BSD 3-Clause "New" or "Revised" License Updated Mar 4, 2022
cjtag_bridge Public archive

🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.

debugging fpga vhdl jtag cjtag ieee1149

VHDL 24 10 BSD 3-Clause "New" or "Revised" License Updated Dec 21, 2021
wb_spi_bridge Public archive

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

flash fpga memory vhdl spi wishbone xip

VHDL 21 1 BSD 3-Clause "New" or "Revised" License Updated Nov 29, 2021
neo430 Public archive

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

open-source microcontroller fpga processor vhdl gcc customizable

VHDL 203 27 BSD 3-Clause "New" or "Revised" License Updated Nov 23, 2021
74xx_discrete_clock Public archive

A retro-style digital clock based on 74xx discrete logic chips

clock retro ttl cmos 7400 4000

6 1 BSD 3-Clause "New" or "Revised" License Updated Oct 22, 2020

stnolting

neorv32 Public

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neorv32-micropython Public

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neorv32-freertos Public

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neorv32-vunit Public

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neorv32-setups Public

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neorv32-verilog Public template

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neorv32-riscof Public template

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neoTRNG Public

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riscv-gcc-prebuilt Public archive

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riscv-arch-test Public

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vhpi_jtag Public

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icarus-verilog-prebuilt Public archive

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neorv32_soc Public

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neorv32-formal Public archive

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riscv-debug-dtm Public archive

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fpga_puf Public archive

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fpga_torture Public archive

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captouch Public archive

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cjtag_bridge Public archive

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wb_spi_bridge Public archive

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neo430 Public archive

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74xx_discrete_clock Public archive

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