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Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Google TPU rebuilt in SystemVerilog: Anatomy of a powerhouse
An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one
Simple example to run Efinix P&R tools from the command line
Tightly Coupled Bus, low complexity, high performance system bus.
Project Peppercorn - GateMate FPGA Bitstream Documentation
32-bit wishbone controller for 16-bit wide data PSRAM/SRAM
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
Development and integration of a comprehensive open-source ecosystem for the design of complex RISC-V System-on-Chip (SoC) architectures, featuring support for embedded FPGA technologies.
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Updated May 15, 2025
VHDL / PoC
Forked from VLSI-EDA/PoCIP Core Library - Published and maintained by the Open Source VHDL Group
Open-source high performance AXI4-based HyperRAM memory controller
Fully functional SpaceWire router. Implemented in VHDL and under continuous development. See manual. Repository also contains a UART-SpaceWire adapter and several implementation files including con…
Woodpecker is a simple, yet powerful CI/CD engine with great extensibility.
Command & Conquer: Remastered Collection
Command and Conquer Tiberian Dawn
Creates a Zephyr Devicetree file from an ARM CMSIS-SVD file
RAVA: an Open Hardware True Random Number Generator based on Avalanche Noise
Run compilers interactively from your web browser and interact with the assembly
crolfes / cheriot-rtos
Forked from CHERIoT-Platform/cheriot-rtosThe RTOS components for the CHERIoT research platform
Ada-based Hardware Abstraction Layer for the neorv32 SoC